//File name  :fifo_port_img_wr_fsm.v
//Version    :V1.0
//Abstract   :通过触发控制写一帧图像写进FIFO的控制功能FSM
module fifo_port_img_wr_fsm 
(
	input                        clk       ,
	input                        rst_n     ,
	input                        sink_sop  ,
	input                        sink_valid,
	input                        sink_eop  ,
	input                        write_trig,//存储一帧的触发信号
    output                       write_done,//标志一帧触发写完成，持续一个时钟高电平
	output                       write_able //代表可以将数据写入fifo的标志，高有效
);
reg state;//0:不可拉高write_able 1:可拉高write_able
wire state_w;//修复过边界问题的state
reg  write_trig_flag;//标志有未处理的write_trig，高有效
reg  write_able_r;
assign state_w = state || (sink_eop && sink_valid);
assign write_able = write_able_r || ((write_trig || write_trig_flag) && sink_sop && sink_valid);
assign write_done = write_able_r && sink_eop && sink_valid;//可写状态下的最后一个写入作为完成标志
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
    begin
    state <= 1'b1;
    end
else
    begin
    state <= (sink_sop && sink_valid)?1'b0:(
    		 (sink_eop && sink_valid)?1'b1:state
    	);
    end
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
    begin
    write_trig_flag <= 1'b0;
    write_able_r <= 1'b0;
    end
else
    begin
    write_trig_flag <= (~state_w && write_trig)?1'b1:(state_w?1'b0:write_trig_flag);
    write_able_r <= (state_w && (write_trig || write_trig_flag))?1'b1:(
    			  (sink_eop && sink_valid && ~(write_trig || write_trig_flag))?1'b0:write_able_r
    	);
    end
end
endmodule 
